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8 Mbit 1.8V SPI Serial Flash
A Microchip Technology Company
SST25WF080
Not Recommended for New Designs
Memory Organization
The SST25WF080 SuperFlash memory arrays are organized in uniform 4 KByte sectors with 16 KByte,
32 KByte, and 64 KByte overlay erasable blocks.
Device Operation
The SST25WF080 are accessed through the SPI (Serial Peripheral Interface) bus compatible protocol.
The SPI bus consist of four control lines; Chip Enable (CE#) is used to select the device, and data is
accessed through the Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK).
The SST25WF080 support both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference
between the two modes, as shown in Figure 4, is the state of the SCK signal when the bus master is in
Stand-by mode and no data is being transferred. The SCK signal is low for Mode 0 and SCK signal is
high for Mode 3. For both modes, the Serial Data In (SI) is sampled at the rising edge of the SCK clock
signal and the Serial Data Output (SO) is driven after the falling edge of the SCK clock signal.
CE#
MODE 3
MODE 3
SCK
SI
MODE 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DON T CAR E
MODE 0
SO
MSB
HIGH IMPEDANCE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
1203 F03.0
Figure 4: SPI Protocol
?2012 Silicon Storage Technology, Inc.
6
DS25024B
03/12
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